Caveat verdict

Verilog Design Flow

verilog-design

88
🟢 Trusted
No high-risk patterns surfaced by the deep scan — automated capability review, not behavioral proof.

Pure workflow/methodology skill for Verilog design; execution sinks are documented example shell commands for running simulators, all matching the stated purpose.

⚠ Flagged for review — coarse, uncorroborated signal, not a confirmed exploit. Review the config yourself before installing.

Automated static analysis — not a human review. Caveat flags capabilities, not confirmed intent, and can produce false positives. Disagree with this verdict? Use Dispute below.

90
security
90
transparency
70
maintenance

Findings (1)

Pattern match medium

Popular HTTP library — network access

references/vcd-analysis.md · code · got

Why the tier is capped

Execution sink present in raw bytes (Hard Floor: class F). Final tier capped at Caution — cannot be lifted by any downgrade, example-payload opt-in, or allowlist.

Permissions & capabilities

No declared permissions — minimal attack surface.

Is this flag fair?

Check another skill Browse the registry Auditing your own skills or configs? Use the API